NVMe Blurs The Lines Between Memory And Storage

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Révision datée du 30 septembre 2025 à 14:17 par LanceDollery (discussion | contributions) (Page créée avec « <br>Personally I don’t suppose we will see the road between memory and storage be all that muddled sooner or later. Yes, 3D XPoint is much more responsive than Flash. Bu... »)
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Personally I don’t suppose we will see the road between memory and storage be all that muddled sooner or later. Yes, 3D XPoint is much more responsive than Flash. But Flash isn’t all that impressive as is. The everyday hard drive has access latencies round 4ms on average. Flash can reach effectively bellow µs latency, however for very small arrays. This is costly and mostly seen in Microcontrollers that execute immediately from their Flash. "Enterprise grade" flash that optimizes at cost/GB could have far larger latency, within the few to tens of µs area. 3D Xpoint is a little bit of a wash. I have seen quoted figures of sub 350ns write latency, however that is likely for a single cell, not an array. Optane modules from Intel on the other hand have typical latencies round 5-15µs, however that is from a "system" perspective, ie, protocol and Memory Wave controller overhead comes into play, as well as one’s software environment.
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DRAM then again has entry latencies around 2-15ns at current. The problem with latency is that it leads to our processor stalling as a consequence of not getting the info in time. One can prefetch, however branches makes prefetching more durable, since what side must you fetch? Department prediction partly solves this challenge. But from a efficiency standpoint, we must always fetch each sides. But if we've extra latency, we need to prefetch even earlier, risking more branches. In different words, peak bandwidth required by our processor increases at an exponential fee compared to latency. A price that's utility dependent as well. Caching may appear like the trivial solution to the difficulty, however the effectivity of cache is proportional to the latency. To a degree, cache is a magic bullet that just makes Memory Wave System latency disappear. But each time an software calls for something that isn’t in cache, then the applying stalls, so long as there may be threads to take its place that even have information to work on, you then won’t have a performance deficit other than thread switching penelties, however in the event you don’t have such threads, then the CPU stalls.



One can be sure that extra threads have their knowledge by just making the cache bigger, however cache is quite a bit costlier than DRAM. In the long run, all of it leads to the fact that growing latency would require an arbitrary quantity extra cache for an analogous system performance. Going from the few ns latency of DRAM to the couple of µs latency of present persistent memory will not be reasonable as an actual replacement for DRAM, even if it reduces its latency to a one hundredth it continues to be not spectacular so far as memory goes. Though, the use of persistent DIMMs for storage caching or Memory Wave System as a "RAM drive" of types nonetheless has major benefits, however for program execution it is laughable. And i don’t suspect this to vary any time soon. But I can see a future the place the primary memory relocates into the CPU. The place the CPU itself has an HBM memory chip or four on it supplying comparatively low latency and excessive bandwidth memory to the CPU, whereas the external buses are used for IO and storage. But this isn’t all that life like in more skilled applications, since some workstation applications actually needs 10’s-100’s of GB of actual RAM to get good efficiency.



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