Direct Memory Access

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With out DMA, when the CPU is using programmed enter/output, it is usually absolutely occupied for the whole duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the switch, then it does different operations while the switch is in progress, and it finally receives an interrupt from the DMA controller (DMAC) when the operation is finished. This characteristic is helpful at any time that the CPU can not keep up with the speed of knowledge switch, or when the CPU must carry out work whereas waiting for a comparatively sluggish I/O knowledge switch. Many hardware systems use DMA, together with disk drive controllers, graphics cards, community cards and sound cards. DMA can be used for intra-chip information transfer in some multi-core processors. Computer systems which have DMA channels can transfer information to and from units with much much less CPU overhead than computers with out DMA channels. Equally, a processing circuitry inside a multi-core processor can switch knowledge to and from its native memory without occupying its processor time, permitting computation and data switch to proceed in parallel.



DMA may also be used for "memory to memory" copying or transferring of information inside memory. DMA can offload expensive memory operations, similar to large copies or scatter-gather operations, from the CPU to a dedicated DMA engine. An implementation example is the I/O Acceleration Expertise. DMA is of interest in network-on-chip and in-memory computing architectures. Commonplace DMA, also known as third-celebration DMA, makes use of a DMA controller. A DMA controller can generate memory addresses and initiate memory read or MemoryWave Guide write cycles. It incorporates several hardware registers that may be written and MemoryWave Guide browse by the CPU. These include a memory tackle register, a byte rely register, and a number of management registers. Depending on what options the DMA controller provides, these control registers might specify some mixture of the supply, the vacation spot, the route of the switch (reading from the I/O system or writing to the I/O device), the dimensions of the transfer unit, and/or the variety of bytes to switch in one burst.



To perform an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of phrases to transfer, and the memory tackle to make use of. The CPU then commands the peripheral device to initiate a knowledge transfer. The DMA controller then provides addresses and browse/write control lines to the system memory. Every time a byte of knowledge is able to be transferred between the peripheral machine and memory, the DMA controller increments its inside deal with register until the full block of information is transferred. Some examples of buses using third-get together DMA are PATA, USB (before USB4), and SATA; nonetheless, their host controllers use bus mastering. In a bus mastering system, also called a primary-get together DMA system, the CPU and peripherals can each be granted management of the memory bus. Where a peripheral can change into a bus grasp, it could actually immediately write to system memory without the involvement of the CPU, offering memory tackle and management indicators as required.



Some measures should be provided to place the processor right into a hold situation so that bus contention does not occur. In burst mode, a complete block of information is transferred in one contiguous sequence. As soon as the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of information in the data block before releasing control of the system buses back to the CPU, however renders the CPU inactive for comparatively lengthy periods of time. The mode can also be called "Block Transfer Mode". The cycle stealing mode is used in techniques wherein the CPU shouldn't be disabled for the size of time needed for burst switch modes. Within the cycle stealing mode, the DMA controller obtains access to the system bus the same approach as in burst mode, utilizing BR (Bus Request) and BG (Bus Grant) indicators, which are the two indicators controlling the interface between the CPU and the DMA controller. Nonetheless, in cycle stealing mode, after one unit of knowledge switch, the control of the system bus is deasserted to the CPU by way of BG.